1. Field of the Invention
Embodiments of the present invention relate to a method of forming a gate structure for a semiconductor device and a method of a forming a cell gate structure for a non-volatile memory device using the same. More particularly, the present invention relates to a method of forming a gate structure having a minute line width for a semiconductor device and a method of forming a cell gate structure for a non-volatile memory device using the same.
2. Description of the Related Art
In general, semiconductor memory devices are classified into a volatile memory device, such as a random-access-memory (RAM) device and a non-volatile memory device, such as a read-only-memory (ROM) device. This classification is based on whether the data stored in the memory device is erased or not when its power is turned off. Data stored in a volatile memory device such as a dynamic RAM (DRAM) and a static RAM (SRAM) are volatile and erased when power is turned off. Data stored in the non-volatile memory device is not erased and its stored charge is maintained over time even though the power is turned off. While the volatile memory device has a high operation speed, the non-volatile memory device has a relatively low operation speed.
Typically, when a plurality of chips is fabricated on a silicon wafer, each of the chips is individually manufactured into the semiconductor memory device. Recently, as semiconductor devices have been highly integrated to fabricate more chips per wafer, a line width of a feature, such as a gate electrode, in a semiconductor device has been correspondingly reduced.
FIGS. 1 and 2 are cross-sectional views illustrating processing steps for a method of forming a cell gate structure for a conventional non-volatile memory device.
Referring to FIG. 1, a tunnel oxide pattern 12, a first conductive pattern 14, a dielectric interlayer pattern 22, a second conductive pattern 24, a metal silicide layer 26 and a hard mask pattern 28 are sequentially stacked on a semiconductor substrate 10 to form a preliminary cell gate structure 30.
In detail, a tunnel oxide layer is formed on the semiconductor substrate 10, and a first conductive layer is formed on the tunnel oxide layer. The first conductive layer is formed to be a floating gate electrode in a subsequent process. Polysilicon doped in-situ with N type or P type impurities is deposited on the tunnel oxide layer to form a first conductive layer.
Then, a dielectric (or insulating) interlayer is formed on the first conductive layer. The dielectric interlayer is multi-layer, including a first oxide layer, a silicon nitride layer, and a second oxide layer that are sequentially stacked on the first conductive layer, which is conventionally known as an ONO structure. A second conductive layer is formed on the dielectric interlayer, and is formed into a control gate electrode in a subsequent process. Polysilicon doped in-situ with N type or P type impurities is also deposited on the dielectric interlayer, thereby forming the second conductive layer.
A metal silicide layer is formed on the second conductive layer for reducing an electrical resistance of a cell gate structure that is to be formed in a subsequent process. In general, a tungsten silicide layer is formed as the metal silicide layer. Then, a hard mask layer is formed on the metal silicide layer for protecting the cell gate structure. In general, a silicon nitride layer is utilized as the hard mask layer.
Then, the hard mask layer, the metal silicide layer, the second conductive layer, the dielectric interlayer, the first conductive layer, and the tunnel oxide layer are sequentially patterned using a conventional photolithography process including an exposing process, a developing process, an etching process, etc. As a result, the tunnel oxide pattern 12, the first conductive pattern 14, the dielectric interlayer pattern 22, the second conductive pattern 24, the metal silicide layer 26, and the hard mask pattern 28 are sequentially stacked on the substrate 10 to thereby form the preliminary cell gate structure 30. The dielectric interlayer pattern 22 includes a first oxide pattern 16, a silicon nitride pattern 18, and a second oxide pattern 20.
Referring to FIG. 2, a re-oxidation process is performed to the substrate 10 including the preliminary cell gate structure 30. Thus an oxide layer 32 is formed on a surface of the substrate 10 and sidewalls of the preliminary cell gate structure 30 to form a cell gate structure 34. The substrate 10, including the preliminary cell gate structure 30, is loaded into a furnace, and a heat treatment is performed on the substrate 10 at a temperature of no less than about 800° C. and at an atmospheric pressure in an oxidation atmosphere. In general, when an etching process is performed on the layers above the substrate 10 to form the preliminary cell gate structure 30, high-energy ions cause damage to the surface of the substrate 10 and the sidewalls of the preliminary cell gate structure 30. The oxide layer formed by the re-oxidation process compensates for the damage and cures the damaged surfaces. In addition, the oxide layer formed by the re-oxidation process reduces the intensity of an electric field generated at an edge portion of the cell gate structure 34, thus the tunnel oxide pattern 12 in the cell gate structure 34 is prevented from breaking down.
However, when the re-oxidation process is completed, oxidants diffuse into both sidewalls of the tunnel oxide pattern 12 to generate a processing failure at the tunnel oxide pattern 12 known as a bird's beak, denoted as ‘a’ in FIG. 2. In addition, the oxidants are also diffused into both sidewalls of the dielectric interlayer pattern 22 to generate another bird's beak, denoted as ‘b’ at the dielectric interlayer pattern 22.
Recently, as semiconductor devices become highly integrated and features of the cell gate structure 34, such as those having a line width ‘c’ are reduced, the bird's beak extends towards central portions of the tunnel oxide pattern 12 and the dielectric interlayer pattern 22. The extended bird's beak increases the thickness of the tunnel oxide pattern 12 and the dielectric interlayer pattern 22, reducing the operating speed of the semiconductor device.
FIG. 3 is a view illustrating the extended bird's beak in the conventional non-volatile memory device.
When the conventional line width c of the cell gate structure 34 shown in FIG. 2 is reduced to a line width c′ shown in FIG. 3, the oxidants are diffused into the central portion of the tunnel oxide pattern 12 as well as the sidewalls, thus the substrate 10 under the central portion of the tunnel oxide pattern 12 and the first conductive pattern 14 on the central portion of the tunnel oxide pattern 12 are also partially oxidized during the re-oxidation process. That is, the bird's beak at sidewalls of the tunnel oxide pattern 12 is extended into the central portion, and an oxidized area is vertically enlarged in the tunnel oxide pattern 12 to increase the thickness of the tunnel oxide pattern 12.
In addition, the oxidants are also diffused into the central portion of the dielectric interlayer pattern 22 as well as the sidewalls, thus the first conductive layer 14 under the central portion of the dielectric interlayer pattern 22 and the second conductive pattern 24 on the central portion of the dielectric interlayer pattern 22 are also partially oxidized during the re-oxidation process. That is, the bird's beak at sidewalls of the dielectric interlayer pattern 22 is extended into the central portion, and an oxidized area is vertically enlarged in the dielectric interlayer pattern 22 to increase a thickness of the dielectric interlayer pattern 22. For these reasons, programming speed and erasing speed are reduced in the non-volatile memory device.
In addition, a programming threshold voltage differs greatly from an erasing threshold voltage due to a difference of line widths of a plurality of cell gate structures in the non-volatile memory device.
From the theoretical view, the line widths of cell gate structures in a conventional non-volatile memory device are all the same, but actual line widths of the cell gate structures are different from each other in an acceptable processing variation. Accordingly, when the re-oxidation process is performed in a cell gate structure having a relatively small line width, the oxidants are diffused further into a central portion of the cell gate structure than when the re-oxidation process is performed in a cell gate structure having a relatively large line width. That is, the bird's beak is more significant at a cell gate structure having a relatively small line width than at a cell gate structure having a relatively large line width, so that the thickness of the tunnel oxide pattern is proportionally greater at a cell gate structure having the relatively small line width. Accordingly, the thickness of the tunnel oxide pattern varies in accordance with the line width of the cell gate structure, and the thickness variation of the tunnel oxide pattern causes the threshold voltage difference.
Reducing the processing time for the re-oxidation process has been suggested for preventing the diffusion of the oxidants into the central portion of the cell gate structure. However, reducing the processing time also causes a problem in that the tunnel oxide pattern is insufficiently cured to deteriorate a bake-retention characteristic of a non-volatile memory device.